As semiconductor devices used for portable telephones and in-vehicle electronic equipment become smaller and require less power, their operating voltages are reduced progressively. Typically, a DC/DC buck converter utilizes a transistor, which is switched by means of PWM control, to supply power to an inductor in order to generate an output voltage that is lower than the input voltage. This kind of buck converter is widely utilized for a switching power supply. For example, U.S. Pat. No. 6,924,633 discloses a PWM controller capable of operating at a high speed.
FIG. 1 is a switching regulator circuit diagram utilizing a conventional buck converter, and FIG. 2 is a timing chart of the circuit shown in FIG. 1. In FIG. 1, output voltage VO is divided at resistors R1 and R2 and input to the negative terminal of PWM comparator COMP1 as feedback voltage VFB. Reference voltage Ref is applied to the positive terminal of PWM comparator COMP1.
Output voltage VO is divided at resistors R3 and R4, and the divided voltage of node N1 is input to the positive terminal of TON comparator COMP2; and node N2, which connects resistor R5 to capacitor C1, is applied to its negative terminal. Resistor R5 is connected to input voltage VIN. One end of capacitor C1 is connected to node N2, and the other end is connected to GND. Drain and source of NMOS transistor QN1 are connected to either end of capacitor C1 in parallel to said capacitor.
Output of TON comparator COMP2 is connected to the reset input of flip-flop circuit FF. Output of PWM comparator COMP1 forms node N4, and node N4 is connected via an inverter to flip-flop circuit FF provided in the subsequent stage. Output of flip-flop circuit FF is connected to the gate of NMOS transistor QN1 via an inverter. Output node N5 of flip-flop circuit FF is connected to output buffer BF1 also. Output node N7 of output buffer BF1 is connected to the gate of NMOS transistor QN2. Drain of transistor QN2 is input terminal VIN, and source of NMOS transistor QN2 is connected to node SW. Node VBST is used for bootstrap. Node SW is connected to inductor L1, and capacitor CO1 constitutes a smoothing filter in conjunction with inductor L1. Output of inductor L1 is connected to output voltage VO, which becomes the output of the switching regulator. Positive terminal of comparator COMP3 is connected to node SW, and its negative terminal is set to a voltage closed to the GND side node voltage of NMOS transistor QN3. Here, D represents a delay element, and BF2 represents an output buffer.
Next, operations of the circuit shown in FIG. 1 will be explained. When feedback voltage VFB input to the negative terminal of PWM comparator COMP1 becomes lower than reference voltage Ref (time t1 in FIG. 2), node N4 as the output of comparator COMP1 is inverted to H level, flip-flop circuit FF of the subsequent stage is set, transistor QN1 constituting a TON timer is turned off in the meantime, and a timer of TON comparator COMP2 is started.
In the case of resistor R5 and capacitor C1 that are connected to the negative terminal of TON comparator COMP2, because resistor R5 and capacitor C1 are connected in series between input voltage VIN and the ground potential, node N2 begins to increase gradually from the GND voltage to generate a TON time until time t2 when it reaches the positive input voltage of TON comparator COMP2. The TON time is inversely proportional to input voltage VIN and proportional to output voltage VO. Once the TON time is reached, that is, when time t2 is reached, node N3, which forms the output of TON comparator COMP2, is inverted to L level; flip-flop circuit FF connected to node N3 is reset; node N6 becomes H level; transistor QN1 is turned on; the potential of node N2 drops; and the TON time ends here.
A TON time is generated at output node N5 of flip-flop circuit FF, it is supplied to output buffer BF1, and transistor QN2 is switched by its output node N7, whereby the TON time is reflected on node SW. TON ∝VO/VIN holds for the TON time.
In the case of the buck switching power supply shown in FIG. 1, power supply conversion efficiency during a standby has been emphasized recently. Reduction of the oscillating frequency of the switching power supply is effective when the efficiency under a light load is to be improved. In addition, in the event of a light load when using a synchronous rectification system, a DCM (Discontinuous Current Mode) system is used to bring output node N8 of output buffer BF2 to L level based on the output of comparator COMP3 so as to turn off low side (Low side) transistor QN3 in order to improve the efficiency under a light load.
However, although the efficiency under a light load can be improved by reducing the oscillating frequency by turning the low side transistor QN3 off, it creates a problem that a ripple voltage reflected upon output voltage VO ends up increased.
Next, the ripple voltage under a light load will be explained. Here, voltage waveforms of on time of transistor QN2, output voltage VO, and feedback voltage VFB are shown in FIG. 3. On time of an ordinary buck switching regulator is decided based on input voltage VIN and output voltage VO, and the on time is expressed by Formulas 1 and 2. Here, cycle is denoted as T, on duty (On duty) is denoted as D, and on time is denoted as TON.[Formula 1]D=VO/VIN  1[Formula 2]TON=T×VO/VIN=T×D  2
Peak current that flows in inductor L1 during the TON time is expressed by Formulas 3 and 4.[Formula 3]Ipeak=1/L×(VIN−VO)×TON  3[Formula 4]Ipeak=1/L×(VIN−VO)×T×VO/VI  4
As for the ripple voltage in the light load mode, when load side transistor QN3 is off, and the energy accumulated in inductor L1 during the TON time is denoted as PL, energy PL is expressed by Formula 5.[Formula 5]PL=½×L×I2peak  5
When this energy PL is moved to capacitor CO1, ripple voltage of capacitor CO1 is expressed by Formula 6.[Formula 6]PL=½×L×I2peak=½×C×V2peak Vpeak=Ipeak×√{square root over ((L/C))}  (6)
From Formulas 3 and 4, the ripple voltage can be expressed by Formulas 7 and 8.[Formula 7]Vpeak=1/L×(VIN−VO)×TON×√{square root over ((L/C))}  (7)[Formula 8]Vpeak=1/L×(VIN−VO)×T×VO/VIN×√{square root over ((L/C))}  (8)
As shown by Formulas 7 and 8, peak voltage Vpeak is affected by TON time. In fact, when L=2.2 μH, input voltage V1=12V, output voltage=1V, C=22 μF, and TON=0.1 μs, peak voltage Vpeak becomes Vpeak=1/L×(VIN−VO)×TON×√{square root over ((L/C))}=0.158V based on Formula 7, which is a fairly high ripple voltage.